• 全部进行finetune会非常耗时。所以提出用adaptor结构保存task-specific的信息。这个adaptor要求要非常小、轻便。
  • 文章提出的adaptor非常简单,由一个layernorm+MLP层组成。先把Feature进行降维,然后再还原。希望这个层里含有domain的信息。
  • 实验发现这个方法非常简单但是能提高效率和精度。

Overview

PFM Mode

  • discontinuous conduction mode with fixed frequency, fixed on-time and variable off-time
  • with zero-bias-current comparator
  • the cross-coupled inverter pair holds the logic levels without taking any power. Very low power is consumed by this comparator since only dynamic current flows through the input pair
  • Vo<VrefV_o<V_{ref}
  • When clk is low, X,Y,Vop,Von**X,Y,V_{op},V_{on}** are pre-charged to supply voltage by M8M11M_8-M_{11}.当clk为低电平的时候,X,Y,Vop,VonX,Y,V_{op},V_{on} 被预先充电到供电电压。
  • When clk is high, input pair Vin,VipV_{in},V_{ip} develops a differential current through pair M1,M2M_1,M_2, leading to a voltage difference between X,YX,Y. 因为输入对Vin,VipV_{in},V_{ip} 的电压不同,导致通过MOS的电流不同,X,YX,Y节点存在压差。
  • Then cross-coupled latch (M3M6M_3-M_6) turns on and regeneration the amplified output signal back to full swing.

PWM Mode and ring-oscillator ADC

  • Due to disturbances from switching activities, a windowed ADC with high-resolution and a reduced quantization range, which is insensitive to switching noise is desirable.

    为了防止开关信号的干扰,需要采用高精度的窗口ADC,这样才能对噪声不敏感。

  • Ring-ADC is invariant under reference voltage changes and can be flexibly adjusted to meet a wide range of application. When the input voltage is reduced, the gain of the ADC
    increases and, hence, the controller gain is also raised proportionally, resulting in an invariant loop gain.

  • The frequency can be controlled by adjusting the supply current to the entire ring.

    M1,M2M_1,M_2 are working at subthreshold region. The differential current will lead to different frequency.

Ce=Mk1gmTADCVeC_e=Mk_1g_mT_{ADC}V_e

RING-MUX DPWM

  • Used for fsamp,PFMf_{samp,PFM}, ADC sampling clock, and PID clock in PWM mode. 用于PFM ADC 和PID的频率,我觉得这里ADC的频率应该是后面数字部分的频率。
    与Delay line类似