- discontinuous conduction mode with fixed frequency, fixed on-time and variable off-time
- with zero-bias-current comparator
- the cross-coupled inverter pair holds the logic levels without taking any power. Very low power is consumed by this comparator since only dynamic current flows through the input pair
- When clk is low, ** are pre-charged to supply voltage by .当clk为低电平的时候， 被预先充电到供电电压。
- When clk is high, input pair develops a differential current through pair , leading to a voltage difference between . 因为输入对 的电压不同，导致通过MOS的电流不同，节点存在压差。
- Then cross-coupled latch () turns on and regeneration the amplified output signal back to full swing.
PWM Mode and ring-oscillator ADC
Due to disturbances from switching activities, a windowed ADC with high-resolution and a reduced quantization range, which is insensitive to switching noise is desirable.
Ring-ADC is invariant under reference voltage changes and can be flexibly adjusted to meet a wide range of application. When the input voltage is reduced, the gain of the ADC
increases and, hence, the controller gain is also raised proportionally, resulting in an invariant loop gain.
The frequency can be controlled by adjusting the supply current to the entire ring.
are working at subthreshold region. The differential current will lead to different frequency.
- Used for , ADC sampling clock, and PID clock in PWM mode. 用于PFM ADC 和PID的频率，我觉得这里ADC的频率应该是后面数字部分的频率。