How to burn your chip

Diodes can’t be forwarded.

Referring to PDK doc, all regular diodes including LV diodes operating in the forward region are not allowed. As the diodes are forwarded, the parasitic BJT operates in forward-active region. Schottky diodes also have substrate injection if the forward voltage is over 0.6V. As empirical evidence has demonstrated, the subtracted leakeage current is as substantial as the forward current.

However, if the schottkey diodes are used for MOS bootstrap, well, they can works well. Because the period of forward operation is limited, it can be neglected. Actually, we do need to consider the leakage current for $\mu$W application.

Switched-Capacitor Hard Charging

Phenomenons

Virtuoso doesn’t warn you the possibility of current damage. Most SC designs encounter the issue of hard charging. When the top and the bottom MOSFETs are on, $C_L$ and $C_{F4}$ are balancing. As shown below, the charging current is up to 6A at beginning.

Fig 2a: The measured Switched-Capacitor topology.

Fig 2b: Simulated hard-charging current.

After the large current, the body diode of the bottom MOSFET is disappear but that of the top MOSFET can still be observed. As measurement result shows, only the bottom MOSFET break down while the top MOSFET works well.

Possible Reason

Due to the channel length modulation, $V_{DS, Top}$ is 4V, larger than $V_{DS, Bot}\approx 0$. That means the top MOSFET can conduct more current than the bottom MOSFET, which causes the bottom MOSFET break-down.

Solution

1. Reduce $V_{DS, Top}$.
   I have measured four $V_{DS, Top}$ cases: 3V, 3.3V, 3.6V, 4V. When $V_{DS, Top}\geq 3.6V$, all chips are burnt. For $V_{DS, Top}= 3.3V$, only a few of chips break down. And all chips works well in the $V_{DS, Top}= 3V$ case.

2. Use larger bottom MOSFETs for new design.

3. Introduce soft-charge techniques.

Reduce crosstalk

The chip area is usually smaller than we actual requirements. The crosstalk in the chip is not avoidable, and the only thing, which can solve the problem, is money. What we can do is to reduce the pcb crosstalk. Fig 3 and Video 1 are referenced from Juliano Mologni’s Linkedin. Spacing between two traces largely impact the crosstalk. If you want to reduce crosstalk, try to enlarge the spacing.

TI also gives some measuremt result about crosstalk reduction.

In my opinion, for low current design, removing the ground plane and increasing the spacing of the traces help to reduce the parasitic capacitance, thus improving the latency and signal quality. And for large current, large power design, ground plane polygon pour is recommended.

Parasitic Csub for fully-integrated designs